Laboratory Notes

Modern Interfaces – Circuit Design, Communication Theory and Convex Optimization

Vladimir Stojanovic
Research Laboratory of Electronics

From game consoles and PCs, to network routers and supercomputers, chip-to-chip communication has emerged as a serious performance bottleneck. Due to the bandwidth limitation of wires, these interfaces have recently grown into full communication micro-systems. In these power constrained systems, maximizing the data rate well into multi-Gb/s range is a complex multidimensional optimization problem.

In the Integrated Systems Group, we are attacking this problem by cutting vertically through the system design hierarchy. By adding coding, we intend to improve both link robustness and energy-efficiency. Unlike in standard communication systems, we investigate design of codes with high energy efficiency and gain with atypical noise sources like jitter, reflections and crosstalk. To do this, we are developing a unique stochastic high-speed link simulator that is able to work with correlated data and characterize the impact of coding down to required bit-error-rates of 10-15 (impossible to achieve with standard Monte-Carlo behavioral simulation).

We are also developing a link architecture that unifies the equalization and clock-and-data recovery (signal processing and synchronization) sub-systems into one higher-performance and more energy-efficient front-end. This link design is made possible by taking advantage of the complex interplay of fractional equalization techniques, innovative adaptive algorithms and high-rate, energy-efficient mixed-signal circuits.

With high-speed links as inspiration, we are working on formulating this complex interplay among different blocks and levels of hierarchy and capturing the interface system design problem as a hierarchical convex optimization (resource allocation) problem. This framework enhances the designer’s ability to analyze and capture the behavior of different circuit blocks and pass the design-space information for each block to the system designer.

Taken together, these techniques can alleviate or completely remove the chip communication bottleneck. By advancing the design of chip-to-chip interfaces through energy-efficient coding and communication techniques, novel architectures and hierarchical optimization, we aim to open the way to creating extremely powerful data networks and computing devices.

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